1. Field
This application relates generally to semiconductor devices having improved thermal characteristics and, in particular, to vertical junction field effect transistors (VJFETs) having improved thermal characteristics and method of making the devices.
2. Background of the Technology
Silicon carbide vertical JFETs typically have source fingers defined over an active area. The width of the source mesa and trench separating any two source fingers are chosen to meet specific device targets such as threshold voltage and blocking gain. For improved specific on-resistance (i.e., resistance normalized over area) and normalized saturated drain current (i.e., Idsat normalized over area), the source fingers are placed at the smallest possible pitch wherein pitch is equal to the sum of the width of the source finger (WSF) and the width of the trench between the source fingers (WT). Placing the fingers at the smallest possible pitch allows the packing of a large number of source fingers in a given active area or given die size.
In certain applications, however, the close proximity of the source fingers resulting from the small pitch results in poor heat dissipation during large current flow through the VJFET. As a result, the temperature of the device can rise. To enable improved heat dissipation and reduce temperature rise in the device, it is preferred that the source fingers be placed further away from each other (i.e., by increasing the trench width). However, a larger trench width can result in a change in the P+ gate implant profile on the source finger sidewall. This in turn can result in changes in the electrical characteristics such as threshold voltage from desired design targets.
Accordingly, there exists a need for VJFETs having improved heat dissipation at high current flow while maintaining the desirable electrical characteristics of devices having small trench widths.